#define OFFSET_x86_EAX   0
#define OFFSET_x86_EBX  12
#define OFFSET_x86_ECX   4
#define OFFSET_x86_EDX   8
#define OFFSET_x86_ESI  24
#define OFFSET_x86_EDI  28
#define OFFSET_x86_EBP  20
#define OFFSET_x86_ESP  16
#define OFFSET_x86_EIP  60

#define OFFSET_amd64_RAX   0
#define OFFSET_amd64_RBX  24
#define OFFSET_amd64_RCX   8
#define OFFSET_amd64_RDX  16
#define OFFSET_amd64_RSI  48
#define OFFSET_amd64_RDI  56
#define OFFSET_amd64_RSP  32
#define OFFSET_amd64_RBP  40
#define OFFSET_amd64_R8   64
#define OFFSET_amd64_R9   72
#define OFFSET_amd64_R10  80
#define OFFSET_amd64_R11  88
#define OFFSET_amd64_R12  96
#define OFFSET_amd64_R13 104
#define OFFSET_amd64_R14 112
#define OFFSET_amd64_R15 120
#define OFFSET_amd64_RIP 168

#define OFFSET_ppc32_GPR0        0
#define OFFSET_ppc32_GPR2        8
#define OFFSET_ppc32_GPR3       12
#define OFFSET_ppc32_GPR4       16
#define OFFSET_ppc32_GPR5       20
#define OFFSET_ppc32_GPR6       24
#define OFFSET_ppc32_GPR7       28
#define OFFSET_ppc32_GPR8       32
#define OFFSET_ppc32_GPR9       36
#define OFFSET_ppc32_GPR10      40
#define OFFSET_ppc32_CIA       896
#define OFFSET_ppc32_CR0_0     913

#define OFFSET_ppc64_GPR0        0
#define OFFSET_ppc64_GPR2       16
#define OFFSET_ppc64_GPR3       24
#define OFFSET_ppc64_GPR4       32
#define OFFSET_ppc64_GPR5       40
#define OFFSET_ppc64_GPR6       48
#define OFFSET_ppc64_GPR7       56
#define OFFSET_ppc64_GPR8       64
#define OFFSET_ppc64_GPR9       72
#define OFFSET_ppc64_GPR10      80
#define OFFSET_ppc64_CIA      1024
#define OFFSET_ppc64_CR0_0    1053

